1. Field of the Invention
The present invention relates in general to memory devices and specifically to a method and apparatus for efficiently correcting defects in memory arrays.
2. Description of the Related Art
Memory arrays, like other electronic circuit components, are susceptible to manufacturing defects and failure. Memory arrays are typically fabricated on an integrated circuit chip, which may be a dedicated memory chip or may include other circuit components. Defects in a memory array may be caused by fabrication errors or improper handling. Environmental factors, age or improper use can cause a memory array to fail at any time.
As a result, techniques have been developed to correct defects in memory arrays. One attempt at correcting defects in arrays includes designing the array to include redundant memory cells. The redundant cells are employed by selectively blowing fuses within an array of fuses connecting the array of cells after determining which cells are defective. When the memory array is operated, storage information is routed to redundant cell locations based on which fuses are blown. In current designs, the arrangement of fuses is such that particular fuses are dedicated to a particular portions of the memory array. Therefore, in order to allow for correction of cells in different portions of the memory array, multiple fuse groups must be implemented. As a result, the number of fuses increases with the number of potential repairable defects, the number of redundant cells and the number of memory array portions.
Static Random Access Memory (SRAMS) arrays employ Field Effect Transistors (FETs) for memory cells. As technologies continually develop to reduce the size of FETs and logic circuitry, technologies for reducing the size of fuses are not improving as quickly. As a result, the area dedicated for fuses on logic chips is increasing in relation to the area dedicated for logic circuitry.
Therefore, there exists a need for a method and apparatus for correcting defects in memory arrays with minimal increase in circuit area.